The present disclosure relates to semiconductor devices formed by three-dimensionally integrating semiconductor integrated circuits with through-vias and manufacturing methods of the devices.
In recent years, in order to proceed with miniaturization of packages with higher integration, higher function and higher speed of semiconductor integrated circuit devices, the industry has been fully studied three-dimensional packaging techniques of stacking a plurality of chips using through silicon vias. One of the techniques is described in for example, Deniz Sabuncuoglu Tezcan, Fabrice Duval, Ole Luhn, Philippe Soussan, and Bart Swinnen, A New Scaled Through Si Via with Polymer Fill for 3D Wafer Level Packaging, Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba (Japan), 2008, pp. 52-53. A manufacturing method of a through silicon via according to a conventional example will be described hereinafter with reference to the document.
FIGS. 13A-13F are cross-sectional views illustrating steps of the manufacturing of the through silicon via according to the conventional example.
As shown in FIG. 13A, after bonding an element formation surface of a silicon device wafer (silicon substrate) 101 to a glass carrier 105 with wax 104, polishing is performed from the back surface (an opposite surface to the element formation surface) of the silicon substrate 101 to thin the silicon substrate 101 to a thickness of about 50 μm.
After that, as shown in FIG. 13B, after a resist 106 having a ring-like pattern is formed on the back surface of the silicon substrate 101 by lithography, the silicon substrate 101 is etched using the resist 106 as a mask. This forms a ring-like groove 151 which reaches the interlayer film 102 covering the element formation surface of the silicon substrate 101. FIG. 14 is a top view of the ring-like groove 151.
Then, as shown in FIG. 13C, after removing the resist 106, an insulating polymer 107 is applied onto the back surface of the silicon substrate 101 to fill the ring-like groove 151.
Next, as shown in FIG. 13D, after a resist 108 having an opening over a circular region surrounded by the ring-like groove 151 is formed on the insulating polymer 107 by lithography, the insulating polymer 107 is etched using the resist 108 as a mask. This removes the portion of the insulating polymer 107, which is positioned in the circular region surrounded by the ring-like groove 151.
After that, as shown in FIG. 13E, the portion of the silicon substrate 101, which is positioned in the circular region surrounded by the ring-like groove 151 is removed by dry etching, thereby forming a via hole 152 reaching the interlayer film 102. Then, the interlayer film 102 on the bottom of the via hole 152 is removed by wet etching. This exposes an interconnect 103 formed on the interlayer film 102 covering the element formation surface of the silicon substrate 101.
Next, after removing the resist 108, a seed layer 109 is formed to cover the side surface and the bottom surface of the via hole 152 as shown in FIG. 13F. Then, after forming a resist pattern 110 having an opening in an interconnect formation region, copper plating is performed to fill the via hole 152 with the copper film 111. Finally, although not shown in the figure, a through silicon via electrode is completed by removing the resist pattern 110 and the underlying seed layer 109.
According to the above-described method of the conventional example, the insulating polymer 107, which has a lower dielectric constant and a lower coefficient of elasticity than an insulating film formed by chemical vapor deposition (CVD), can be formed between the silicon substrate 101 and the through-via (the copper film 111). This reduces parasitic capacitance caused by the through-via. Furthermore, since the insulating polymer 107 serves as a buffer material, stress mismatch caused by a difference in the coefficient of thermal expansion between the silicon substrate 101 and the through-via (copper film 111) can be reduced.